1. Field
The embodiment relates to signal waveform equalizer circuits and receiver circuits, which may relate to a signal waveform equalizer circuit for shaping signal waveforms distorted due to transmission, and a receiver circuit provided with the signal waveform equalizer circuit.
2. Description of the Related Art
In recent years, high-speed serial interfaces enabling over 1-Gbps data transfer between, for example, LSIs (Large Scale Integrated circuits), such as Serial-ATA (Advanced Technology Attachment), PCI (Peripheral Component Interconnect)-Express and 10 Gbit-Ethernet (registered trademark), have come into wide use.
Where a data signal is transmitted at high speed through a transmission line with large loss, however, the signal components, especially the high-frequency signal components are significantly lost, with the result that the waveform of the signal arriving at the receiver circuit is distorted, giving rise to a problem that the receiver circuit fails to properly receive the data. To solve the problem, a signal waveform equalizer circuit (equalizer circuit) has been used at the receiving end to amplify only the high-frequency components of the signal, thereby reproducing the original waveform.
FIG. 8 shows an example of a conventional equalizer circuit.
The conventional equalizer circuit 70 has pull-up resistors 71 and 72, n-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors; hereinafter abbreviated as nMOS(s)) 73 and 74, a resistor 75, a capacitor 76, and constant current sources 77 and 78.
The pull-up resistor 71 is connected between a high potential-side power supply terminal VDD and the drain of the nMOS 73, and the pull-up resistor 72 is connected between the power supply terminal VDD and the drain of the nMOS 74. Differential signals are input to the equalizer circuit. Namely, a positive-phase input signal INP is input to the gate of the nMOS 73, and a negative-phase input signal INN is input to the gate of the nMOS 74. The resistor 75 and the capacitor 76 are connected in parallel between the sources of the nMOSs 73 and 74. Also, the source of the nMOS 73 is connected through the constant current source 77 to a low potential-side power supply terminal VSS, and the source of the nMOS 74 is connected through the constant current source 78 to the power supply terminal VSS. The potential between the drain of the nMOS 74 and the pull-up resistor 72 and the potential between the drain of the nMOS 73 and the pull-up resistor 71 are output as positive- and negative-phase output signals OUTP and OUTN, respectively, from the equalizer circuit 70.
FIG. 9 illustrates operating waveforms of the conventional equalizer circuit.
Specifically, the figure shows input data before transmission to the receiver circuit, data after the transmission (i.e., input signals (positive- and negative-phase input signals INP and INN) to the equalizer circuit 70), and output signals (positive- and negative-phase output signals OUTP and OUTN) of the equalizer circuit 70. In each graph, the horizontal and vertical axes indicate time T and voltage V, respectively.
As illustrated, the transmitted signals (positive- and negative-phase input signals INP and INN) are subject to loss because of the transmission over a transmission line, and their waveforms are distorted. For example, the difference in level between the positive- and negative-phase input signals INP and INN decreases, as shown in the figure.
Where the thus distorted positive- and negative-phase input signals INP and INN are input to the equalizer circuit 70 shown in FIG. 8, the high-frequency components of the signals are amplified by means of the circuit constant of the resistor 75 and capacitor 76, and positive- and negative-phase output signals OUTP and OUTN whose waveforms have been shaped (equalized), as shown in FIG. 9, are output.
In the conventional equalizer circuit 70 of FIG. 8, however, since the input signals (positive- and negative-phase input signals INP and INN) are applied to the gates of the nMOSs 73 and 74, the input signal voltages must at least be higher than a threshold at which the nMOSs 73 and 74 are switched on, in order to permit a sufficient current to flow. Accordingly, the equalizer circuit as it stands is unable to handle input signals with a center voltage of 0 V, as used in the PCI-Express standard.
Conventionally, therefore, the center voltage of the input signals had to be converted before input to the equalizer circuit 70.
FIG. 10 shows part of a receiver circuit including a center voltage converter circuit as a circuit preceding the equalizer circuit.
The center voltage converter circuit 80 has capacitors 81 and 82, and resistors 83 and 84. The positive- and negative-phase input signals INP and INN are input through the capacitors 81 and 82, respectively, to the equalizer circuit 70. The node between the capacitor 81 and the equalizer circuit 70 is connected to one end of the resistor 83, and the node between the capacitor 82 and the equalizer circuit 70 is connected to one end of the resistor 84. A bias voltage is applied to the other ends of the resistors 83 and 84. Because of the capacitive coupling, the center voltage 0 V of the positive- and negative-phase input signals INP and INN can be converted to the bias voltage.
Where the center voltage converter circuit 80 is used to pull up the center voltage, however, the problem described below arises.
FIG. 11 shows the manner of how the center voltage converter circuit outputs signals by pulling up their center voltage, wherein the horizontal and vertical axes indicate time T and voltage V, respectively. The figure also shows the input signals (positive- and negative-phase input signals INP and INN) whose center voltage is not pulled up yet, namely, the input signals with the center voltage 0 V.
As seen from FIG. 11, where the center voltage is pulled up by means of capacitive coupling, the amplitudes of the positive- and negative-phase input signals INP and INN decrease with the lapse of time if the input data and thus the input signal voltages remain the same, with the result that the voltage difference between the differential input signals diminishes, making it difficult to receive the data.
Also, if the frequency of occurrences “1” and “0” in the input data is biased toward “1” or “0”, the signal amplitudes become imbalanced, making it hard to receive either of the input data. Accordingly, restrictions need to be imposed on the use (or the specification) such that “1” and “0” of data should occur with an equal probability during a fixed period of time.
In the conventional receiver circuit, the equalizer circuit 70 is followed by a data latch circuit for receiving and latching the positive- and negative-phase output signals OUTP and OUTN (see, e.g., Unexamined Japanese Patent Publication No. 2003-318726).
FIG. 12 shows an exemplary configuration of the data latch circuit.
The data latch circuit 90 has p-channel MOSFETs (hereinafter abbreviated as pMOS(s)) 91 to 94, and nMOSs 95 to 99.
The pMOSs 91 and 92 have their sources connected to the power supply terminal VDD, and their drains connected to each other as well as to the gates of the pMOS 93 and nMOS 96 and the drain of the nMOS 95. A clock signal CK is input to the gate of the pMOS 91.
The pMOSs 93 and 94 have their sources connected to the power supply terminal VDD, and their drains connected to each other as well as to the gates of the pMOS 92 and nMOS 95 and the drain of the nMOS 96. The clock signal CK is input to the gate of the pMOS 94.
The sources of the nMOSs 97 and 98 are connected to each other as well as to the drain of the nMOS 99. Out of the output signals of the equalizer circuit 70, the positive-phase output signal OUTP is input to the gate of the nMOS 97, and the negative-phase output signal OUTN is input to the gate of the nMOS 98.
The nMOS 99 has its source connected to the power supply terminal VSS, and its gate input with the clock signal CK.
The data latch circuit 90 outputs positive- and negative-phase latch output signals, of which the positive-phase latch output signal LATOP is derived from the node between the drain of the nMOS 96 and the drains of the pMOSs 93 and 94, while the negative-phase latch output signal LATON is derived from the node between the drain of the nMOS 95 and the drains of the pMOSs 91 and 92.
In the data latch circuit 90 configured as above, the output signals (positive- and negative-phase output signals OUTP and OUTN) of the equalizer circuit 70 are input to the gates of the nMOSs 97 and 98, and when the clock signal CK rises, the input data is held by a latch constituted by the pMOSs 92 and 93 and the nMOSs 95 and 96.
In order for the data to be correctly latched, however, the voltage level of either of the positive- and negative-phase output signals OUTP and OUTN must at least be higher than a threshold at which the nMOSs 97 and 98 of the data latch circuit 90 are switched on. Thus, the circuit constant of the equalizer circuit 70 needs to be tuned so that the above voltage level can be secured in all processing and operating conditions.
Such tuning of the circuit constant, however, restricts the operating range (operable bandwidth) of the equalizer circuit 70, giving rise to a problem that the required characteristics cannot be obtained.
In the conventional equalizer circuit 70, for example, if the resistances of the pull-up resistors 71 and 72 are high because of variations caused during the manufacture or due to temperature fluctuation, the voltages of the positive- and negative-phase output signals OUTP and OUTN lower. Thus, taking account of such situations, the circuit constant is tuned through simulation so that the output voltage levels of the equalizer circuit 70 may be high enough to enable the data latch circuit 90 to hold data.
Conversely, if the resistances of the pull-up resistors are low, then the voltages of the positive- and negative-phase output signals OUTP and OUTN become too high, so that the differential voltage swing becomes small or the voltage for discriminating the data held by the data latch circuit 90 deviates from an appropriate level enabling high-sensitivity decision, deteriorating the characteristics as a whole.
To solve the problem, there have been proposed methods in which the equalizer circuit 70 is followed by a differential amplifier circuit or is additionally provided with a feedback circuit.
FIG. 13 shows part of a receiver circuit in which the conventional equalizer circuit is additionally provided with a feedback circuit.
In the figure, like reference signs are used to denote like elements of the equalizer circuit 70 shown in FIG. 8. The feedback circuit 100 has a comparator 101 and resistors 102 and 103. As illustrated, the center voltage of the positive- and negative-phase output signals OUTP and OUTN is obtained by means of resistance splitting. The center voltage is input to the positive-phase input terminal of the comparator 101, and a reference voltage is input to the negative-phase input terminal of same. In accordance with the result of the comparison between the center voltage and the reference voltage, the resistances of pull-up resistors 71a and 72a, which are variable resistors as illustrated, are adjusted so that the output signals may have appropriate voltage levels.
The addition of the feedback circuit 100, however, leads to complexity of circuitry as well as to increase in area and current consumption.
Meanwhile, Unexamined Japanese Patent Publication No. 2005-260287, for example, discloses an amplifier which is provided with an input voltage monitor circuit and in which, when the center voltage (common voltage) of the input signal varies, the gate voltage of a MOS is controlled to prevent the gain from becoming unstable.
As explained above, to enable the conventional equalizer circuit to handle input signals with the center voltage 0 V, as used in the PCI-Express standard, an extra circuit needs to be additionally provided and also restrictions must be placed on the input signals. Also, the conventional receiver circuit involves significant labor in tuning the circuit constant by means of simulation in order to allow the data latch circuit succeeding the equalizer circuit to hold data. Further, since a feedback circuit or a differential amplifier circuit needs to be additionally provided, a problem arises in that the scale of circuitry enlarges.